1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a thin film magnetic memory device capable of random access and including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of nonvolatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the performance of the MRAM device is significantly improved by using tunnel magnetic resistive elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 13 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 13, the MTJ memory cell includes a tunnel magnetic resistive element TMR having its electric resistance value varying according to the storage data level, and an access transistor ATR. The access transistor ATR is formed from a field effect transistor, and is coupled between the tunnel magnetic resistive element TMR and the ground voltage VSS.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the storage data level in the data read and write operations.
FIG. 14 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 14, the tunnel magnetic resistive element TMR has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, sometimes simply referred to as xe2x80x9cfixed magnetic layer FLxe2x80x9d), and a magnetic layer VL having a free magnetic field (hereinafter, sometimes simply referred to as xe2x80x9cfree magnetic layer VLxe2x80x9d). A tunnel barrier TB of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. According to the storage data level, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL has been written to the free magnetic layer VL in a non-volatile manner.
In the data read operation, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed from the bit line BL, tunnel magnetic resistive element TMR, access transistor ATR and ground voltage VSS. The sense current Is is supplied as a constant current from a not-shown control circuit.
The electric resistance value of the tunnel magnetic resistive element TMR varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. More specifically, when the fixed magnetic layer FL and the free magnetic layer VL have the same magnetic field direction, the tunnel magnetic resistive element TMR has a smaller electric resistance value as compared to the case where both magnetic layers have different magnetic field directions. The electric resistance values of the tunnel magnetic resistive element corresponding to the storage data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are herein indicated by R1 and R0, respectively (where R1 greater than R0 and R1=R0+xcex94R).
The electric resistance value of the tunnel magnetic resistive element TMR thus varies according to an externally applied magnetic field. This enables data storage to be conducted based on the variation characteristics of the electric resistance value of the tunnel magnetic resistive element TMR. In general, the tunnel magnetic resistive element TMR that is applied to the MRAM devices has an electric resistance value in the range from about several kilo-ohms to about several tens of kilo-ohms.
A voltage change in the tunnel magnetic resistive element TMR due to the sense current Is varies depending on the magnetic field direction stored in the free magnetic layer VL. Therefore, by starting supply of the sense current Is with the bit line BL precharged to a high voltage, the storage data level in the MTJ memory cell can be read by monitoring a change in voltage level on the bit line BL.
FIG. 15 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 15, in the data write operation, the read word line RWL is inactivated, so that the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is supplied to the write word line WWL and the bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write currents flowing through the write word line WWL and the bit line BL.
FIG. 16 is a conceptual diagram illustrating the relation between the respective directions of the data write current and the magnetic field in the data write operation.
Referring to FIG. 16, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(BL) and H(WWL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the tunnel magnetic resistive element TMR by the data write operation, a current must be applied to both the write word line WWL and bit line BL. Once stored in the tunnel magnetic resistive element TMR, the magnetic field direction, i.e., the storage data, is retained therein in a non-volatile manner until another data write operation is conducted.
The sense current Is flows through the bit line BL in the data read operation. However, the sense current Is is generally set to a value that is about one to two orders smaller than the data write current. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten by the sense current Is during the data read operation.
The aforementioned technical documents disclose the technology of forming an MRAM device, a random access memory, by integrating such MTJ memory cells on a semiconductor substrate.
FIG. 17 is a conceptual diagram showing the MTJ memory cells arranged in a matrix in an integrated manner.
Referring to FIG. 17, a highly integrated MRAM device can be realized by arranging the MTJ memory cells in a matrix on the semiconductor substrate. FIG. 17 shows the MTJ memory cells arranged in n rows by m columns (where n, m is a natural number). Herein, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are provided for the nxc3x97m MTJ memory cells.
In the data read operation, one of the read word lines RWL1 to RWLn is selectively activated, so that the memory cells on the selected memory cell row (hereinafter, sometimes simply referred to as xe2x80x9cselected rowxe2x80x9d) are electrically coupled between the bit lines BL1 to BLm and the ground voltage VSS, respectively. As a result, the voltage on each bit line BL1 to BLm changes according to the storage data level in a corresponding memory cell.
Thus, the storage data level of the selected memory cell can be read by comparing the voltage on the bit line of the selected memory cell column (hereinafter, sometimes simply referred to as xe2x80x9cselected columnxe2x80x9d) with a prescribed reference voltage using a sense amplifier or the like.
A dummy memory cell is generally used to produce such a reference voltage. For example, a dummy resistance having an electric resistance value Rd corresponding to an intermediate value of the electric resistance values R1 and R0 can be used as a dummy memory cell for use in the data read operation from the MTJ memory cell. The electric resistance values R1 and R0 respectively correspond to the electric resistance values of the MTJ memory cell storing the data xe2x80x9c1 (H level)xe2x80x9d and xe2x80x9c0 (L level)xe2x80x9d. The reference voltage can be produced by supplying the same sense current Is as that of the MTJ memory cell to the dummy resistance.
However, the data read operation requires the operation of charging and discharging a data line such as bit line to which a tunnel magnetic resistive element TMR having a relatively high electric resistance value is connected, thereby possibly making it difficult to increase the speed of the data read operation.
As described in the aforementioned technical documents, as a bias voltage applied to both ends of the magnetic tunnel junction, i.e., both ends of the tunnel magnetic resistive element TMR, is increased, a change in electric resistance value, xcex94R, is reduced that corresponds to the relative relation of the magnetization direction between the fixed magnetic layer FL and the free magnetic layer VL, i.e., that corresponds to the storage data level. Therefore, as the voltage applied to both ends of the MTJ memory cell is increased in the data read operation, the voltage on the bit line does not noticeably change corresponding to the storage data level. This may possibly hinder the speed and stability of the data read operation.
Moreover, accuracy of the reference voltage is significantly affected by the electric resistance value of the dummy resistance in the dummy memory cell. Therefore, it is difficult to accurately set the reference voltage according to manufacturing variation.
It is an object of the present invention to provide a thin film magnetic memory device capable of high-speed, stable data read operation.
A thin film magnetic memory device according to the present invention includes a plurality of magnetic memory cells, a first data line, a first precharging circuit, a first read driving circuit, and a first charge transfer feedback amplifier portion, and an amplifier portion. Each of the plurality of magnetic memory cells has its electric resistance value varying according to a storage data level written therein by an applied magnetic field. The first data line is electrically coupled to a first voltage through a selected one of the plurality of magnetic memory cells in data read operation. The first precharging circuit sets the first data line to a precharge voltage before the data read operation. The first read driving circuit supplies a data read current to the first data line in the data read operation. The first charge transfer feedback amplifier portion is provided between the first data line and a first internal node, for retaining a voltage on the first data line and producing a first output voltage onto the first internal node according to an integral value of the data read current flowing through the first data line. The amplifier portion produces read data based on the voltage on the first internal node.
Preferably, the precharge voltage is the first voltage, and the first read driving circuit couples the first data line to a second voltage in the data read operation.
Preferably, the first charge transfer feedback amplifier portion includes an operational amplifier for amplifying a voltage difference between first and second input nodes to produce the first output voltage onto the first internal node, a charge transfer portion coupled between the first data line and the first input node, for transmitting a voltage change on the first data line due to the data read current to the first input node, and a charge feedback portion coupled between the first internal node and the first data line, for supplying charges according to a change in the first output voltage so as to cancel the voltage change on the first data line from the first voltage. The precharge voltage is applied to the second input node.
Preferably, the plurality of magnetic memory cells are arranged in a matrix. The thin film magnetic memory device further includes: a plurality of word lines provided respectively corresponding to magnetic memory cell rows; a plurality of bit lines provided respectively corresponding to magnetic memory cell columns; and a column selection portion for connecting one of the plurality of bit lines that is electrically coupled to the selected magnetic memory cell to the first data line.
Alternatively, the thin film magnetic memory device preferably further includes: a dummy memory cell having an intermediate electric resistance value of two electric resistance values of each magnetic memory cell, the two electric resistance values respectively corresponding to two storage data levels; a second data line electrically coupled to the first voltage through the dummy memory cell in the data read operation; a second precharging circuit for setting the second data line to the precharge voltage before the data read operation; a second read driving circuit for supplying a data read current to the second data line in the data read operation; and a second charge transfer feedback amplifier portion provided between the second data line and a second internal node, for retaining a voltage on the second data line and producing a second output voltage onto the second internal node according to an integral value of the data read current flowing through the second data line. The amplifier portion produces the read data according to a voltage difference between the first and second internal nodes.
In particular, the precharge voltage is the first voltage, and the first and second read driving circuits respectively couple the first and second data lines to a second voltage in the data read operation.
Preferably, the thin film magnetic memory device further includes: a dummy memory cell having an intermediate electric resistance value of two electric resistance values of each magnetic memory cell, the two electric resistance values respectively corresponding to two storage data levels; a second data line electrically coupled to the first voltage through the dummy memory cell in the data read operation; a second precharging circuit for setting the second data line to the precharge voltage before the data read operation; a second read driving circuit for supplying the data read current to the second data line in the data read operation; a second charge transfer feedback amplifier portion provided between the second data line and a second internal node, for maintaining a voltage on the second data line and producing a second output voltage onto the second internal node according to an integral value of the data read current flowing through the second data line; and a charge feedback portion coupled between the second internal node and the first data line, for feeding back with a reversed polarity a change in the second output voltage to the first data line.
In particular, the precharge voltage is the first voltage, and the first and second read driving circuits respectively couple the first and second data lines to a second voltage in the data read operation.
Such a thin film magnetic memory device enables suppression of a bias voltage that is applied to both ends of the selected magnetic memory cell in the data read operation. Accordingly, a change in electric resistance value in the magnetic memory cell according to the storage data level is more likely to appear, allowing for improved speed and stability of the data read operation.
Moreover, providing the bit lines and the first data line in a hierarchical manner enables a plurality of magnetic memory cells arranged in a matrix to share the circuitry associated with the data read operation.
Furthermore, the data read operation is conducted based on comparison between the dummy memory cell and the selected magnetic memory cell. Therefore, the data read operation can be accurately conducted within a margin of the timing of sensing the first output voltage from the first charge transfer feedback amplifier portion, thereby allowing for further stabilized data read operation. In particular, the voltage difference between the first and second data lines is amplified to produce the first output voltage through the charge feedback portion, thereby allowing for simplified circuit structure of the amplifier portion for producing the data.
A thin film magnetic memory device according to another aspect of the present invention includes a plurality of magnetic memory cells, a first data line, a dummy memory cell, a second data line, and a data read circuit. Each of the plurality of magnetic memory cells stores data written by an applied magnetic field. Each magnetic memory cell includes a magnetic storage portion having one of a first electric resistance value and a second electric resistance value that is larger than the first electric resistance value, according to a level of the storage data, and a memory cell selection gate connected in series with the magnetic storage portion, and rendered conductive when selected. The first data line is electrically coupled to the magnetic storage portion and the conductive memory cell selection gate of a selected magnetic memory cell and receives a data read current in data read operation. The dummy memory cell has an intermediate electric resistance value of the first and second electric resistance values. The dummy memory cell includes a dummy resistance portion having the first electric resistance value, and a dummy memory cell selection gate connected in series with the dummy resistance portion, and rendered conductive when selected. The second data line is electrically coupled to the dummy resistance portion and the conductive dummy memory cell selection gate and receives the data read current in the data read operation. The data read circuit produces read data based on a voltage change on the first and second data lines. An electric resistance value of the conductive dummy memory cell selection gate is larger than a third electric resistance value and is smaller than a sum of a difference between the second and first electric resistance values and the third electric resistance value. The third electric resistance value is an electric resistance value of the conductive memory cell selection gate.
Preferably, each of the memory cell selection gates includes a first field effect transistor, and the dummy memory cell selection gate includes a second field effect transistor having at least one of its gate width and gate length being different from that of the first field effect transistor.
Alternatively, each of the memory cell selection gates preferably includes a first field effect transistor, and the dummy memory cell selection gate preferably includes a second field effect transistor having the third electric resistance value when rendered conductive, and a third field effect transistor connected in series with the second field effect transistor and having an electric resistance value smaller than the difference when rendered conductive. The second field effect transistor is designed in common with the first field effect transistor.
Preferably, the dummy resistance portion includes a magnetic storage portion for storing a data level corresponding to the first electric resistance value. The magnetic storage portion included in the dummy resistance portion has a same structure as that of the magnetic storage portion included in each magnetic memory cell.
Such a thin film magnetic memory device enables the magnetic storage portion in the magnetic memory cell and the dummy resistance portion in the dummy memory cell to be formed on the same array by using the magnetic storage portions of common design. Accordingly, the electric resistance value of the dummy memory cell can be appropriately set while allowing manufacturing variation. As a result, a read operation margin can be ensured regardless of the manufacturing variation.
A thin film magnetic memory device according to a further aspect of the present invention includes a plurality of magnetic memory cells, a dummy memory cell, a first data line, a second data line, a data read circuit, and a dummy resistance adding circuit. Each of the plurality of magnetic memory cells stores data written by an applied magnetic field. The dummy memory cell is compared with a selected one of the plurality of magnetic memory cells in data read operation. Each of the magnetic memory cells and the dummy memory cell include a magnetic storage portion having one of a first electric resistance value and a second electric resistance value that is larger than the first electric resistance value, according to a level of the storage data, and a memory cell selection gate connected in series with the magnetic storage portion, and rendered conductive when selected. The magnetic storage portion included in the dummy memory cell stores data at a level corresponding to the first electric resistance value. The first data line is electrically coupled to one of the selected magnetic memory cell and the dummy memory cell in the data read operation. The second data line is electrically coupled to the other of the selected magnetic memory cell and the dummy memory cell in the data read operation. The data read circuit supplies a data read current to each of the first and second data lines and produces read data based on a voltage change on the first and second data lines. The dummy resistance adding circuit selectively connects a resistance portion in series with one of the first and second data lines that is electrically coupled to the dummy memory cell. The resistance portion has an electric resistance value smaller than a difference between the first and second electric resistance values.
Preferably, the resistance portion includes a field effect transistor receiving a variable control voltage at its gate.
Alternatively, the dummy resistance adding circuit preferably selects one of the first and second data lines to which the resistance portion is connected, according to a part of a row address.
Such a thin film magnetic memory device enables the magnetic memory cell and the dummy memory cell to have the same structure. Accordingly, a read operation margin can be ensured according to manufacturing variation of the magnetic memory cells.
Moreover, the resistance value of the resistance portion that is connected in series with the dummy memory cell can be adjusted according to the variable control voltage. Therefore, a read operation margin can be ensured according to manufacturing variation of the difference between the electric resistance values of the magnetic storage portion that corresponds to the difference in storage data level.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.